In manufacturing an electronic device, a plasma etching is performed to transfer a pattern of a mask to an underlying film. As for the mask, a resist mask is generally used. The resist mask is formed by a photolithography technique. Accordingly, the critical dimension of the pattern formed in the layer to be etched relies on the resolution limit of the resist mask formed by the photolithography technique.
In recent years, with the high integration of an electronic device, there has been a demand for forming a pattern having a dimension smaller than the resolution limit of the resist mask. Thus, a technique has been suggested which adjusts a width of an opening defined by the resist mask by depositing a silicon oxide film on the resist mask. Japanese Patent Laid-Open Publication No. 2011-082560 discloses this technique.
In the technique disclosed in Japanese Patent Laid-Open Publication No. 2011-082560, the silicon oxide film is formed on the resist mask according to an atomic layer deposition (ALD) method. Specifically, aminosilane gas and activated oxygen species are alternately supplied to a workpiece having the resist mask.